Paper Title
Low Power Mirror Sequence March Test Algorithm For Static Random Access Memories
Abstract
Abstract— Low power design has emerged as the most essential field of work in VLSI system design. At the same time power
dissipation in testing became more critical while designing a testable integrated circuit. During testing the design will
consume much more power compared with normal functional mode. A novel Static Random Access Memory Testing scheme
is presented in this paper, which can test memories using March test algorithms with a great reduction in test power. Testing
in March algorithms is done marching from top to bottom and from bottom to top in a sequential manner. Like this each byte
in the memory is tested multiple number of times. Sequencing in these testing algorithms is of binary sequencing. Because of
the binary sequencing multiple number of bits toggle in each address sequence. If the binary sequencing is replaced with
Single bit change address sequencing, number of transitions in the sequence reduces. There by power consumption in the
testing reduces enormously. March Y based Built in Self-Test (BIST) algorithm is described using Verilog HDL language and
is simulated using Xilinx ISE. Spartan-3E FPGA is used to implement the architecture.