Paper Title :Implementation Of High Speed Pipelined ADC Architecture For I-UWB Receiver
Author :D. Reena, K. Lokesh Krishna, T. Ramashri, D. Srihari
Article Citation :D. Reena ,K. Lokesh Krishna ,T. Ramashri ,D. Srihari ,
(2013 ) " Implementation Of High Speed Pipelined ADC Architecture For I-UWB Receiver " ,
International Journal of Electrical, Electronics and Data Communication (IJEEDC) ,
pp. 35-41,
Volume-1,Issue-3
Abstract : In this work, a 4-bit pipelined ADC that provides the high speed conversion needed in UWB applications with
sampling frequency of the order 60 Gbps is proposed. The pipelined ADC designed uses a high speed 1-bit comparator, wide
band operational amplifier, sampling circuit and a high speed buffer. The individual blocks are designed using 130nm
CMOS low power library cells. The individual blocks are designed to operate at a frequency greater than 60 Gbps sampling
rate. In order to operate increase the operating frequency of the pipelined ADC, Specific new design techniques/algorithms
such as power-efficient, capacitor ratio-independent conversion scheme, a pipeline stage-scaling algorithm, a nested CMOS
gain-boosting technique, an amplifier and comparator sharing technique, and the use of minimum channel- length, thin oxide
transistors with clock bootstrapping and in-line switch techniques are adopted.
Type : Research paper
Published : Volume-1,Issue-3
DOIONLINE NO - IJEEDC-IRAJ-DOIONLINE-150
View Here
Copyright: © Institute of Research and Journals
|
 |
| |
 |
PDF |
| |
Viewed - 51 |
| |
Published on 2014-01-20 |
|